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Preliminary Technical Data
FEATURES
Low power (250 A @ 5 V) single 16-bit nanoDACTM True 12-bit accuracy guaranteed Tiny 8-lead SOT-23/MSOP package Power-down to 200 nA @ 5 V, 50 nA @ 3 V Power-on-reset to zero/midscale 2.7 V to 5.5 V power supply Guaranteed 16-bit monotonic by design 3 power-down functions Serial interface with Schmitt-triggered inputs Rail-to-rail operation SYNC interrupt facility
2.7 V to 5.5 V, 250 A, Rail-to-Rail Output 16-Bit nanoDACTM D/A in a SOT-23 AD5662
FUNCTIONAL BLOCK DIAGRAM
VREF GND VDD POWER-ON RESET
AD5662
VFB REF(+) 16-BIT DAC
DAC REGISTER
OUTPUT BUFFER
VOUT
INPUT CONTROL LOGIC
POWER-DOWN CONTROL LOGIC
RESISTOR NETWORK
04777-0-001
APPLICATIONS
Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators
SYNC
SCLK
DIN
Figure 1.
GENERAL DESCRIPTION
The AD5662 parts are a member of the nanoDACTM family of devices. They are low power, single, 16-bit buffered voltage-out DACs. All devices operate from a single 2.7 V to 5.5 V, and are guaranteed monotonic by design. The AD5662 requires an external reference voltage to set the output range of the DAC. The part incorporates a power-onreset circuit that ensures the DAC output powers up to 0 V (AD5662x-1) or midscale (AD5662x-2), and remains there until a valid write takes place. The part contains a power-down feature that reduces the current consumption of the device to 200 nA at 5 V, and provides software selectable output loads while in power-down mode. The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The power consumption is 0.7 mW at 5 V, reducing to 1 W in power-down mode. The AD5662's on-chip precision output amplifier allows rail-torail output swing to be achieved. The AD5662 utilizes a versatile 3-wire serial interface that operates at clock rates up to 30 MHz, and is compatible with standard SPITM, QSPITM, MICROWIRETM, and DSP interface standards.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
The AD5662 is designed with new technology, and is the next generation to the AD53xx family.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. 16-bit DAC; true 12-bit accuracy guaranteed. Available in 8-lead SOT-23 and 8-lead MSOP package. Power-on-reset to zero or midscale. Low power. Operates with 2.7 V to 5.5 V supply. Typically consumes 0.35 mW at 3 V and 0.7 mW at 5 V, making it ideal for battery-powered applications. Power-down capability. When powered down, the DAC typically consumes 50 nA at 3 V and 200 nA at 5 V. 10 s settling time.
Description 3 V/5 V 12-/14-/16-bit DAC with internal ref in Sot-23
5. 6.
RELATED DEVICES
Part No. AD5620/AD5640/AD5660
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD5662 TABLE OF CONTENTS
Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Description .............................. 7 Terminology ...................................................................................... 8 Typical Performance Characteristics ............................................. 9 General Description ....................................................................... 13 D/A Section................................................................................. 13 Resistor String ............................................................................. 13 Output Amplifier........................................................................ 13 Serial Interface ............................................................................ 13
Preliminary Technical Data
Input Shift Register .................................................................... 13 SYNC Interrupt .......................................................................... 13 Power-On-Reset ......................................................................... 14 Power-Down Modes .................................................................. 14 Microprocessor Interfacing....................................................... 15 Applications..................................................................................... 16 Using REF19x as a Power Supply for AD5662 ....................... 16 Bipolar Operation Using the AD5662 ..................................... 16 Using AD5662 with an Opto-Isolated Interface .................... 17 Power Supply Bypassing and Grounding................................ 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18
REVISION HISTORY
10/04--Revision PrA
Rev. PrA | Page 2 of 20
Preliminary Technical Data SPECIFICATIONS
AD5662
VDD = 2.7 V to 5.5 V; RL = 2 k to GND; CL = 200 pF to GND; VREF = VDD: all specifications TMIN to TMAX, unless otherwise noted. Table 1.
Parameter STATIC PERFORMANCE2 Resolution Relative Accuracy Differential Nonlinearity Zero Code Error Full-Scale Error Offset Error Gain Error Zero Code Error Drift3 Gain Temperature Coefficient3 DC Power Supply Rejection Ratio OUTPUT CHARACTERISTICS3 Output Voltage Range Output Voltage Settling Time A Grade Min Typ Max 16 32 1 1 -0.15 5 -1.25 10 1.25 1 -0.15 B Grade Min Typ Max 16 16 1 5 -1.25 10 1.25 Unit Bits LSB LSB mV % FSR mV % FSR V/C ppm dB B Version1 Conditions/Comments
See Figure 4. Guaranteed monotonic by design. See Figure 5. All 0s loaded to DAC register. See Figure 8. All 1s loaded to DAC register. See Figure 8.
2 2.5 -100
2 2.5 -100
Of FSR/C DAC code = midscale; VDD = 5V/3V 10%
0 8
VDD 10
0 8
VDD 10
V s s V/s nF nF nV/Hz Vp-p dB nV-s nV-s mA s s
Slew Rate Capacitive Load Stability Output Noise Spectral Density Output Noise (0.1 Hz to 10 Hz) THD, Total Harmonic Distortion Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short-Circuit Current4 Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance 0
1.5 2 10 80 10 -80 5 0.1 0.5 30 4 10 35 20 150 1 0.8 2 3 45 30 VDD
1.5 2 10 80 10 -80 5 0.1 0.5 30 4 10 35 20 0 150 1 0.8 2 3 45 30 VDD
1/4 to 3/4 scale; RL = 2 k; 0 pF < CL < 200 pF. See Figure 18. 1 LSB Settling 1/4 to 3/4 scale RL = RL = 2 k DAC code = midscale,10 kHz DAC code = midscale VREF = 2 V 300 mV p-p, f = 5 kHz 1 LSB change around major carry. See Figure 21.
VDD = 5 V, 3 V Coming out of power-down mode. VDD = 5 V VDD = 3 V VREF = VDD = 5 V VREF = VDD = 3.6 V
A A V k A V V pF
VDD = 5 V, 3 V VDD = 5 V, 3 V
Rev. PrA | Page 3 of 20
AD5662
Parameter POWER REQUIREMENTS VDD IDD (Normal Mode) VDD= 4.5 V to 5.5 V VDD= 2.7 V to 3.6 V IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V POWER EFFICIENCY IOUT/IDD A Grade Min Typ Max 2.7 250 240 0.2 0.05 89 5.5 400 390 1 1 B Grade Min Typ Max 2.7 250 240 0.2 0.05 89 5.5 400 390 1 1 Unit V A A A A %
Preliminary Technical Data
B Version1 Conditions/Comments All digital inputs at 0 V or VDD DAC active and excluding load current VIH = VDD and VIL = GND VIH = VDD and VIL = GND VIH = VDD and VIL = GND VIH = VDD and VIL = GND ILOAD = 2 mA. VDD = 5 V
1 2
Temperature ranges are as follows: B version: -40C to +105C, typical at +25C. DC specifications tested with the outputs unloaded unless otherwise stated. Linearity calculated using a reduced code range of 512 to 65024. 3 Guaranteed by design and characterization, not production tested. 4 Output unloaded.
Rev. PrA | Page 4 of 20
Preliminary Technical Data TIMING CHARACTERISTICS
AD5662
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter t11 t2 t3 t4 t5 t6 t7 t8 t9 t10 Limit at TMIN, TMAX VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V 50 33 13 13 13 13 0 0 5 5 4.5 4.5 0 0 50 33 13 13 0 0 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to sclk fall ignore SCLK falling edge to SYNC fall ignore
1
Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V, and 20 MHz at VDD = 2.7 V to 3.6 V.
t10
SCLK
t1
t9
t8
SYNC
t4
t3
t2
t7
t5
DIN
DB2 3
DB0
Figure 2. Serial Write Operation
Rev. PrA | Page 5 of 20
04777-0-002
t6
AD5662 ABSOLUTE MAXIMUM RATINGS
TA = 25C unless otherwise noted. Table 3.
Parameter VDD to GND Digital Input Voltage to GND VOUT to GND VREF to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature (TJ Max) SOT-23 Package Power Dissipation JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +105C -65C to +150C 150C (TJ MAX - TA)/JA 240C/W 215C 220C
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 6 of 20
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTION
VDD 1 VREF 2
8
AD5662
GND
VOUT 4
5
SYNC
Figure 3. MSOP/SOT-23 Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 Mnemonic VDD VREF VFB VOUT SYNC Function Power Supply Input. These parts can be operated from 2.5 V to 5.5 V. VDD should be decoupled to GND. Reference Voltage Input. Feedback Connection for the Output Amplifier. Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Ground Reference Point for All Circuitry on the Part.
6 7 8
SCLK DIN GND
Rev. PrA | Page 7 of 20
04777-0-003
7 DIN TOP VIEW VFB 3 (Not to Scale) 6 SCLK
AD5662
AD5662 TERMINOLOGY
Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL versus code plot can be seen in Figure 4. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL versus code plot can be seen in Figure 5. Zero-Code Error Zero-code error is a measure of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5662 because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. A plot of zero-code error versus temperature can be seen in Figure 8. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD - 1 LSB. Full-scale error is expressed in percent of full-scale range. A plot of full-scale error versus temperature can be seen in Figure 8.
Preliminary Technical Data
Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range. Total Unadjusted Error Total unadjusted error (TUE) is a measure of the output error, taking all the various errors into account. A typical TUE versus code plot can be seen in Figure 6. Zero-Code Error Drift This is a measure of the change in zero-code error with a change in temperature. It is expressed in V/C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 21. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s, and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa.
Rev. PrA | Page 8 of 20
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
AD5662
Figure 4. Typical INL Plot
Figure 7. INL Error and DNL Error vs. Temperature
Figure 5. Typical DNL Plot
Figure 8. Zero-Scale Error and Full-Scale Error vs. Temperature
Figure 6. Typical Total Unadjusted Error Plot
Figure 9. IDD Histogram with VDD = 3 V and VDD = 5 V
Rev. PrA | Page 9 of 20
AD5662
Preliminary Technical Data
Figure 10. Source and Sink Current Capability with VDD = 3 V
Figure 13. Supply Current vs. Temperature
Figure 11. Source and Sink Current Capability with VDD = 5 V
Figure 14. Supply Current vs. Supply Voltage
Figure 12. Supply Current vs. Code
Figure 15. Power-Down Current vs. Supply Voltage
Rev. PrA | Page 10 of 20
Preliminary Technical Data
AD5662
Figure 16. Supply Current vs. Logic Input Voltage
Figure 19. Power-On Reset to 0 V
SCLK 2
VOUT
VDD = VREF = 5V TA = 25C EXITS PD TO MIDSCALE
1 CH1 500mV CH2 5.0V M1.0s 500MS/s 2.0ns/pt
Figure 17. Full-Scale Settling Time
Figure 20. Exiting Power-Down to Midscale
2.502500 2.502250 2.502000 2.501750 2.501500 2.501250 VDD = VREF = 5V TA = 25C 13nS/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE (0x8000 0x7FFF) GLITCH IMPULSE = 2.723nV.s
AMPLITUDE
2.501000 2.500750 2.500500 2.500250 2.500000 2.499750 2.499500 2.499250 2.499000 2.498750 0 50 100
04777-0-005
Figure 18. Half-Scale Settling Time
150 200 250 300 350 SAMPLE NUMBER
400
450 500 550
Figure 21. Digital-to-Analog Glitch Impulse (Negative)
Rev. PrA | Page 11 of 20
04777-0-004
AD5662
2.500400 2.500300 2.500200 2.500100 2.500000 14 16 VREF = VDD TA = 25C
Preliminary Technical Data
VDD = 3V 12
TIME (S)
AMPLITUDE
2.499900 2.499800 2.499700 2.499600 2.499500 2.499400 2.499300 2.499200 2.499100 0 50 100
10
8 VDD = VREF = 5V TA = 25C 13nS/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE (7FFFh 8000h) GLITCH IMPULSE = 1.271nV.s 150 200 250 300 350 SAMPLE NUMBER 400
VDD = 5V
04777-0-006
4 0 1 2 3 4 5 6 7 CAPACITANCE (nF) 8 9
450 500 550
10
Figure 22. Digital-to-Analog Glitch Impulse (Positive)
Figure 25. Settling Time vs. Capacitive Load
2.500250 2.500200 2.500150 2.500100 2.500050 VDD = VREF = 5V TA = 25C 20nS/SAMPLE NUMBER DAC LOADED WITH MIDSCALE DIGITAL FEEDTHROUGH = 0.06nV.s
VDD = VREF = 5V TA = 25C DAC LOADED WITH MIDSCALE
AMPLITUDE
2.500000 2.499950 2.499900 2.499850 2.499800 2.499750
04777-0-007
1
2.499650 2.499600 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400
Y AXIS = 2V/DIV X AXIS = 4s/DIV
450 500 550
Figure 23. Digital Feedthrough
Figure 26. 0.1 Hz to 10 Hz Output Noise Plot
-20 -30 -40 -50 VDD = 5V TA = 25C DAC LOADED WITH FULLSCALE VREF = 2V 0.3Vp-p
dB
-60 -70 -80 -90 -100 2k 4k Hz 6k 8k
04777-0-008
10k
Figure 24. Total Harmonic Distortion
Rev. PrA | Page 12 of 20
04777-0-010
2.499700
04777-0-009
6
Preliminary Technical Data GENERAL DESCRIPTION
D/A SECTION
The AD5662 DAC is fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 27 shows a block diagram of the DAC architecture.
VDD VFB REF (+) DAC REGISTER RESISTOR STRING REF (-) OUTPUT AMPLIFIER VOUT
AD5662
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range of 0 V to VDD. It is capable of driving a load of 2 k in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 10 and Figure 11. The slew rate is 1 V/s with a half-scale settling time of 8 s with the output unloaded.
SERIAL INTERFACE
The AD5662 has a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5662compatible with high speed DSPs. On the 24th falling clock edge, the last data bit is clocked in and the programmed function is executed (i.e., a change in DAC register contents and/or a change in the mode of operation). At this stage, the SYNC line may be kept low or be brought high. In either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Since the SYNC buffer draws more current when VIN = 2.4 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation. As is mentioned previously, however, it must be brought high again just before the next write sequence.
GND
Figure 27. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal output voltage is given by
D VOUT = VREF x 65,536
where D is the decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535.
RESISTOR STRING
The resistor string section is shown in Figure 28. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
04777-0-022
INPUT SHIFT REGISTER
R
R
R
TO OUTPUT AMPLIFIER
The input shift register is 24 bits wide (see Figure 29). The first six bits are don't cares. The next two are control bits that control the part's mode of operation (normal mode or any one of three power-down modes). See the Power-On Reset section for a more complete description of the various modes. The next 16 bits are the data bits. These are transferred to the DAC register on the 24th falling edge of SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the 24th falling edge. However if SYNC is brought high before the 24th falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs--see Figure 30.
R
Figure 28. Resistor String
04777-0-023
R
Rev. PrA | Page 13 of 20
AD5662
DB23 (MSB) X X X X X X PD1 PD0 D13 D12 D11 D10 D9 D8 D7 D6
Preliminary Technical Data
DBO (LSB) D5 D4 D3 D2 D1 D0
DATA BITS
0 0 1 1
0 1 0 1
NORMAL OPERATION 1 k TO GND 100 k TO GND THREE-STATE POWER-DOWN MODES
04777-0-024
Figure 29. Input Register Contents
SCLK
SYNC
INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 24TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 24TH FALLING EDGE
Figure 30. SYNC Interrupt Facility
POWER-ON RESET
The AD5662 family contains a power-on-reset circuit that controls the output voltage during power-up. The AD5662x-1 DAC output powers up to 0 V, and the AD5662x-2 DAC output powers up to midscale. The output remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up.
POWER-DOWN MODES
The AD5662 contains four separate modes of operation. These modes are software-programmable by setting two bits (DB17 and DB16) in the control register. Table 5 shows how the state of the bits corresponds to the device's mode of operation. Table 5. Modes of Operation for the AD5662
DB17 0 0 1 1 DB16 0 1 0 1 Operating Mode Normal Operation Power-Down Modes 1 k to GND 100 k to GND Three-State
When both bits are set to 0, the part works normally with its normal power consumption of 250 A at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. There are three different options. The output is connected internally to GND through a 1 k or 100 k resistor, or is left open-circuited (three-state). The output stage is illustrated in Figure 31.
VFB
AMPLIFIER RESISTOR STRING DAC
VOUT
Figure 31. Output Stage during Power-Down
The bias generator, the output amplifier, the resistor string, and other associated linear circuitry are all shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 2.5 s for VDD = 5 V and 5 s for VDD = 3 V. See Figure 20 for a plot.
Rev. PrA | Page 14 of 20
04777-0-026
POWER-DOWN CIRCUITRY
RESISTOR NETWORK
04777-0-025
DIN
DB23
DB0
DB23
DB0
Preliminary Technical Data
MICROPROCESSOR INTERFACING
AD5662 to ADSP-2101/ADSP-2103 Interface
Figure 32 shows a serial interface between the AD5662 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, 24-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled.
ADSP-2101/ ADSP-2103*
AD5662
AD5662 to 80C51/80L51 Interface
Figure 34 shows a serial interface between the AD5662 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TXD of the 80C51/80L51 drives SCLK of the AD5662, while RXD drives the serial data line of the part. The SYNC signal is again derived from a bit programmable pin on the port. In this case, port line P3.3 is used. When data is to be transmitted to the AD5662, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD5662 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account.
80C51/80L51*
AD5662*
TFS DT SCLK
SYNC DIN SCLK
04777-0-027
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5662*
Figure 32. AD5662 to ADSP-2101/ADSP-2103 Interface
AD5662 to 68HC11/68L11 Interface
Figure 33 shows a serial interface between the AD5662 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5662, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/68L11 should be configured with its CPOL bit as a 0 and its CPHA bit as a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/ 68L11 is configured as described above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data to the AD5662, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure.
68HC11/68L11*
P3.3 TXD RXD
SYNC SCLK DIN
04777-0-029 04777-0-030
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 34. AD5662 to 80C51/80L51 Interface
AD5662 to MICROWIRE Interface
Figure 35 shows an interface between the AD5320 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5320 on the rising edge of the SK.
MICROWIRE*
AD5662*
CS SK SO
SYNC SCLK DIN
AD5662*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 35. AD5662 to MICROWIRE Interface
PC7 SCK MOSI SYNC SCLK DIN
04777-0-028
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 33. AD5662 to 68HC11/68L11 Interface
Rev. PrA | Page 15 of 20
AD5662 APPLICATIONS
USING REF19x AS A POWER SUPPLY FOR AD5662
Because the supply current required by the AD5662 is extremely low, an alternative option is to use a REF19x voltage reference (REF195 for 5 V, REF193 for 3 V) to supply the required voltage to the part--see Figure 36. This is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 V or 3 V, for example, 15 V. The REF19x outputs a steady supply voltage for the AD5662. If the low dropout REF195 is used, it must supply 250 A of current to the AD5662. This is with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current required (with a 5 k load on the DAC output) is 250 A + (5 V/5 k) = 1.25 mA The load regulation of the REF195 is typically 2 ppm/mA, which results in a 2.5 ppm (12.5 V) error for the 1.25 mA current drawn from it. This corresponds to a 0.164 LSB error.
+15V +5V
Preliminary Technical Data
BIPOLAR OPERATION USING THE AD5662
The AD5662 has been designed for single-supply operation but a bipolar output range is also possible using the circuit in Figure 37. The circuit below gives an output voltage range of 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. The output voltage for any input code can be calculated as follows:
D R1 + R2 R2 VO = V DD x x - V DD x R1 65,536 R1 where D represents the input code in decimal (0 to 65535). With VDD = 5 V, R1 = R2 = 10 k,
10 x D VO = - 5V 65,536 This is an output voltage range of 5 V, with 0x0000 corresponding to a -5 V output and 0xFFFF corresponding to a 5 V output.
REF195
250A
R2 = 10k +5V
04777-0-031
THREE-WIRE SERIAL INTERFACE
SYNC SCLK DIN
AD5662
VOUT = 0V TO 5V
+5V
R1 = 10k AD820/ OP295 VDD 10F 0.1F VOUT 5V
Figure 36. REF195 as Power Supply to AD5662
AD5662
-5V
THREE-WIRE SERIAL INTERFACE
Figure 37. Bipolar Operation with the AD5662
Rev. PrA | Page 16 of 20
04777-0-032
Preliminary Technical Data
USING AD5662 WITH A GALVANICALLY ISOLATED INTERFACE
In process-control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur in the area where the DAC is functioning. Isocouplers provide isolation in excess of 3 kV. The AD5662 uses a 3-wire serial logic interface so the ADuM130x 3-channel digital isolator provides the required isolation (see Figure 38). The power supply to the part also needs to be isolated. This is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5662.
+5V REGULATOR POWER 10F 0.1F
AD5662
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5662 should have separate analog and digital sections, each having its own area of the board. If the AD5662 is in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5662. The power supply to the AD5662 should be bypassed with 10 F and 0.1 F capacitors. The capacitors should be located as close as possible to the device, with the 0.1 F capacitor ideally right up against the device. The 10 F capacitors are the tantalum bead type. It is important that the 0.1 F capacitor has low effective series resistance (ESR) and effective series inductance (ESI), for example, common ceramic types of capacitors. This 0.1 F capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.
VDD 10k SCLK SCLK VDD
VDD 10k SYNC SYNC
AD5662
VOUT
VDD 10k DATA DIN GND
04777-0-033
Figure 38. AD5662 with an Opto-Isolated Interface
Rev. PrA | Page 17 of 20
AD5662 OUTLINE DIMENSIONS
2.90 BSC
8 7 6 5
Preliminary Technical Data
1.60 BSC
1 2 3 4
2.80 BSC
PIN 1 INDICATOR 0.65 BSC 1.30 1.15 0.90 1.95 BSC
1.45 MAX 0.38 0.22
0.22 0.08 8 4 0
0.15 MAX
SEATING PLANE
0.60 0.45 0.30
COMPLIANT TO JEDEC STANDARDS MO-178BA
Figure 39. 8-Lead SOT-23 (RJ-8) Dimensions shown in millimeters
3.00 BSC
8
5
3.00 BSC
4
4.90 BSC
PIN 1 0.65 BSC 1.10 MAX 8 0 0.80 0.60 0.40
0.15 0.00 0.38 0.22 COPLANARITY 0.10
0.23 0.08 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 40. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5662ARJ-1 AD5662ARJ-2 AD5662ARM AD5662BRJ-1 AD5662BRJ-2 AD5662BRM Grade A A A B B B Power-On Reset to Code Zero Midscale Zero Zero Midscale Zero Branding D38 D39 D38 D36 D37 D36 Package Options1 RJ-8 RJ-8 RM-8 RJ-8 RJ-8 RM-8 Description 32 LSB INL 32 LSB INL 32 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
1
RJ = SOT-23, RM = MSOP
Rev. PrA | Page 18 of 20
Preliminary Technical Data NOTES
AD5662
Rev. PrA | Page 19 of 20
AD5662 NOTES
Preliminary Technical Data
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04777-0-10/04(PrA)
Rev. PrA | Page 20 of 20

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